1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a recessed channel and a manufacturing method of the same.
2. Description of the Related Art
A damascene gate is considered as a highly promising electrode structure of a high-performance MOS transistor. The damascene gate is formed in such a manner that a gate insulation film and a gate electrode are buried in a trace of a removed dummy gate (a mask for use in forming source/drain regions), and is characterized in that a recessed channel can be formed easily therein.
For forming the recessed channel, a channel region is etched so as to be positioned lower than a diffusion layer region. Raising up a diffusion layer in effect makes it possible to reduce a short channel effect (a phenomenon that an absolute value of a threshold value voltage lowers in accordance with the reduction in gate length in a microscopic transistor). There is disclosed an art in which a silicon active layer on a bottom of a gate trench from which a dummy gate has been removed is made thinner by a RIE method or the like, whereby a recessed channel is formed (see JP-A 2003-298060).